1. Field of the Invention
The present invention relates to silicon carbide layers, silicon nitride layers, and organosilicate layers and, more particularly to methods of forming silicon carbide layers, silicon nitride layers and organosilicate layers.
2. Background of the Invention
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit densities. The demands for greater circuit densities necessitates a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g., sub-micron dimensions), the materials used to fabricate such components contribute to the electrical performance of such components. For example, low resistivity metal interconnects (e.g., aluminum and copper) provide conductive paths between the components on integrated circuits.
Typically, the metal interconnects are electrically isolated from each other by a bulk insulating material. When the distance between adjacent metal interconnects and/or the thickness of the bulk insulating material has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross-talk and/or resistance-capacitance (RC) delay, which degrades the overall performance of the integrated circuit.
In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant bulk insulating materials (e.g., dielectric constants less than about 3.5) are needed. Typically, bulk insulating materials with dielectric constants less than about 3.5 are tensile materials (e.g., tensile stresses greater than about 108 dynes/cm2). Examples of low dielectric constant bulk insulating materials include silicon dioxide (SiO2), silicate glass, and organosilicates, among others.
In addition, a low dielectric constant (low k) barrier layer often separates the metal interconnects from the bulk insulating materials. The barrier layer minimizes the diffusion of the metal from the interconnects into the bulk insulating material. Diffusion of the metal from the interconnects into the bulk insulating material is undesirable because such diffusion can affect the electrical performance of the integrated circuit (e.g., cross-talk and/or RC delay), or render it inoperative.
The demands for greater integrated circuit densities also impose demands on the process sequences used for integrated circuit manufacture. For example, in process sequences using conventional lithographic techniques, a layer of energy sensitive resist is formed over a stack of material layers on a substrate. Many of these underlying material layers are reflective to ultraviolet light. Such reflections can distort the dimensions of features such as lines and vias that are formed in the energy sensitive resist material.
One technique proposed to minimize reflections from an underlying material layer uses an anti-reflective coating (ARC). The ARC is formed over the reflective material layer prior to resist patterning. The ARC suppresses the reflections off the underlying material layer during resist imaging, providing accurate pattern replication in the layer of energy sensitive resist.
Silicon carbide (SiC) has been suggested for use as a barrier layer and/or ARC on integrated circuits, since silicon carbide layers can have a low dielectric constant (dielectric constant less than about 5.5), are good metal diffusion barriers and can have good light absorption properties. Silicon nitride has also been suggested as a barrier layer and/or ARC, since it also has good metal diffusion barrier and can have good light absorption properties.
Thus, there is an ongoing need for silicon carbide layers, silicon nitride layers, and organosilicate layers with low dielectric constants as well as improved film characteristics.
A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a fluorine source in the presence of an electric field.
A method of forming a silicon nitride layer for use in integrated circuit fabrication processes is provided. The silicon nitride layer is formed by reacting a gas mixture comprising a silicon source, a nitrogen source, and a fluorine source in the presence of an electric field.
A method of forming an organosilicate layer for use in integrated circuit fabrication processes is provided. The organosilicate layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, an oxygen source and a fluorine source in the presence of an electric field.
The silicon carbide layer, the silicon nitride layer and the organosilicate layer are all compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as both a hard mask and a barrier layer for fabricating integrated circuit structures such as, for example, a dual damascene structure. For such an embodiment, a preferred process sequence includes depositing a silicon carbide barrier layer on a metal layer formed on a substrate. After the silicon carbide barrier layer is deposited on the substrate a first dielectric layer is formed thereon. A silicon carbide hard mask layer is formed on the first dielectric layer. The silicon carbide hard mask is patterned to define vias therein. Thereafter, a second dielectric layer is formed on the patterned silicon carbide hard mask layer. The second dielectric layer is patterned to define interconnects therein. The interconnects formed in the second dielectric layer are positioned over the vias defined in the silicon carbide hard mask layer. After the second dielectric layer is patterned, the vias defined in the silicon carbide hard mask layer are transferred into the first dielectric layer. Thereafter, the dual damascene structure is completed by filling the vias and interconnects with a conductive material.
Alternatively, a silicon nitride layer may be used as both a hard mask and a barrier layer for fabricating the dual damascene structure. For such an embodiment, a preferred process sequence includes depositing a silicon nitride barrier layer on a metal layer formed on a substrate. After the silicon nitride barrier layer is deposited on the substrate a first dielectric layer is formed thereon. A silicon nitride hard mask layer is formed on the first dielectric layer. The silicon nitride hard mask is patterned to define vias therein. Thereafter, a second dielectric layer is formed on the patterned silicon nitride hard mask layer. The second dielectric layer is patterned to define interconnects therein. The interconnects formed in the second dielectric layer are positioned over the vias defined in the silicon nitride hard mask layer. After the second dielectric layer is patterned, the vias defined in the silicon nitride hard mask layer are transferred into the first dielectric layer. Thereafter, the dual damascene structure is completed by filling the vias and interconnects with a conductive material.
In another integrated circuit fabrication process, an organosilicate material may be used as the first and second dielectric layers in the dual damascene structure. For such an embodiment, a preferred process sequence includes depositing a barrier layer on a metal layer formed on a substrate. After the barrier layer is deposited on the substrate a first organosilicate layer is formed thereon. A hard mask layer is formed on the first organosilicate layer. The hard mask is patterned to define vias therein. Thereafter, a second organosilicate layer is formed on the patterned hard mask layer. The second organosilicate layer is patterned to define interconnects therein. The interconnects formed in the second organosilicate layer are positioned over the vias defined in the hard mask layer. After the second organosilicate layer is patterned, the vias defined in the hard mask layer are transferred into the first organosilicate layer. Thereafter, the dual damascene structure is completed by filling the vias and interconnects with a conductive material.
The silicon carbide layer, the silicon nitride layer, or the organosilicate may also function as an anti-reflective coating (ARC) for deep ultraviolet (DUV) lithography. For such an embodiment, a preferred process sequence includes forming a silicon carbide layer (alternatively a silicon nitride layer or an organosilicate layer) on a substrate. The silicon carbide layer (alternatively the silicon nitride layer or the organosilicate layer) has a refractive index (n) in a range of about 1.6 to about 2.2 and an absorption coefficient (xcexa) in a range of about 0.1 to about 0.9 at wavelengths less than about 250 nm (nanometers). The refractive index (n) and the absorption coefficient (xcexa) are tunable, in that they can be varied in the desired range as a function of the composition of the gas mixture during silicon carbide layer formation. After the silicon carbide layer (alternatively the silicon nitride layer or the organosilicate layer) is formed on the substrate, a layer of energy sensitive resist material is formed thereon. A pattern is defined in the energy sensitive resist at a wavelength less than about 250 nm. Thereafter, the pattern defined in the energy sensitive resist material is transferred into the silicon carbide layer (alternatively the silicon nitride layer or the organosilicate layer) and, optionally, into the substrate.